ProkOS Ada GPU Research

Project code: PADA

Purpose

This repository contains the durable research and future engineering artifacts for evaluating a custom graphics card based on NVIDIA AD103 / Ada with increased VRAM.

The current project phase is feasibility research. Custom schematic and PCB design are explicitly out of scope until the memory and firmware constraints are understood well enough to support an engineering decision.

Current research questions

The project must establish, from inspectable evidence where possible:

• AD103 memory-controller, FB-partition and subchannel topology;
• RAMCFG / strap behaviour and supported memory geometries;
• VBIOS and firmware constraints affecting memory configuration;
• supported DRAM density, organization, ranks and chip-select behaviour;
• GDDR6 / GDDR6X package, vendor and PHY compatibility;
• realistic VRAM configurations, including 32 / 48 / 64 / 96 GB feasibility;
• legally accessible service documentation that can recover board and memory-side implementation details.

Confirmed starting facts

The following facts are currently confirmed:

• full AD103 has eight 32-bit memory controllers, for a 256-bit memory interface;
• GeForce RTX 4080 uses AD103 with GDDR6X;
• public service-document leads exist for ASUS RTX 4080 boards CG1396BS and CG1396PBI;
• the project must distinguish evidence from engineering inference.

Known service-document leads include:

• ASUS ROG Strix RTX 4080, project CG1396BS;
• ASUS TUF RTX 4080, project CG1396PBI.

Paid or access-restricted service files are not included in this repository by default.

Evidence levels

Research notes must label material as:

• confirmed: directly supported by inspectable evidence;
• source lead: a potentially relevant source is known, but decisive content is not yet inspected;
• hypothesis: an engineering inference that still requires verification.

Stage 1: AD103 memory-topology evidence pack

Current Stage 1 scope:

1. obtain at least two independent legal RTX 4080 PCB/schematic/boardview sources where possible;
2. recover FB partition and memory-subchannel naming/mapping from evidence;
3. identify RAMCFG, strap and memory-configuration signals where available;
4. document populated and DNP memory footprints on stock 16 GB boards where evidence permits;
5. keep confirmed facts, source leads and hypotheses separate;
6. maintain a durable source index and evidence notes as research progresses.

Current engineering boundary

The project does not yet select:

• a final VRAM capacity;
• a specific DRAM part or vendor;
• PCB stack-up or layer count;
• VRM architecture;
• CAD toolchain;
• cooling architecture.

Those decisions require separate evidence and explicit agreement.

Working rules

Repository-specific working rules are defined in AGENTS.md.

Repository operations are performed only through ProkOS FPlug V2.1 typed operations.